Designing circuit layouts includes accounting for parasitic capacitance and parasitic resistance of elements within an interconnect structure. Parasitic capacitance results from conductive features of the interconnect structure unintentionally functioning as a capacitor. Parasitic resistance results from unintentional resistance to current flow at interfaces of various elements. Parasitic capacitance and parasitic resistance impact a performance of the circuit including speed of the circuit, power consumption of the circuit and other operating parameters. Unavoidable production variation causes size and spacing of elements within the interconnect structure to vary from an intended design. These variations in turn change the parasitic capacitance and parasitic resistance of the circuit layout. Average and extreme values of these variations are called process corners and are used in designing the circuit layout.
In some approaches, a techfile is generated for a combination of each process corner of the parasitic capacitance and the parasitic resistance. For example, a typical, i.e., average, parasitic capacitance corner combined with a best, i.e., lowest, parasitic resistance corner; or a worst, i.e., highest, parasitic capacitance combined with a worst parasitic resistance corner; etc. During designing of the circuit layout, a user includes information from this group of techfiles to determine whether the circuit layout will perform a function for which the circuit is designed.